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DS1020 Programmable 8-Bit Silicon Delay Line
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FEATURES
All-silicon time delay Models with 0.15 ns, 0.25 ns, 0.5 ns, 1 ns, and 2 ns steps Programmable using 3-wire serial port or 8-bit parallel port Leading and trailing edge accuracy Standard 16-pin DIP or 16-pin SOIC Economical Auto-insertable, low profile Low-power CMOS TTL/CMOS-compatible Vapor phase, IR and wave solderable
IN E Q/PO P1 P2 P3 P4 GND
PIN ASSIGNMENT
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC OUT S P7 P6 C P5 D IN E Q/PO P1 P2 P3 P4 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC OUT S P7 P6 C P5 D
DS1020 16-pin DIP (300-mil) See Mech. Drawings Section
DS1020S 16-pin SOIC (300-mil) See Mech. Drawings Section
PIN DESCRIPTION
IN P0-P7 GND OUT VCC S E C Q D - Delay Input - Parallel Program Pins - Ground - Delay Output - +5 Volts - Mode Select - Enable - Serial Port Clock - Serial Data Output - Serial Data Input
DESCRIPTION
The DS1020 Programmable 8-Bit Silicon Delay Line consists of an 8-bit, user-programmable CMOS silicon integrated circuit. Delay values, programmed using either the 3-wire serial port or the 8-bit parallel port, can be varied over 256 equal steps. The fastest model (-15) offers a maximum delay of 48.25 ns with an incremental delay of 0.15 ns, while the slowest model (-200) has a maximum delay of 520 ns with an incremental delay of 2 ns. All models have an inherent (step-zero) delay of 10 ns. After the user-determined delay, the input logic state is reproduced at the output without inversion. The DS1020 is TTL- and CMOS-compatible, capable of driving 10 74LS-type loads, and features both rising and falling edge accuracy. The all-CMOS DS1020 integrated circuit has been designed as a reliable, economic alternative to hybrid programmable delay lines. It is offered in a standard 16-pin auto-insertable DIP and a space-saving surface mount 16-pin SOIC.
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111799
DS1020
PARALLEL MODE (S=1)
In the PARALLEL programming mode, the output of the DS1020 will reproduce the logic state of the input after a delay determined by the state of the eight program input pins P0 - P7. The parallel inputs can be programmed using DC levels or computer-generated data. For infrequent modification of the delay value, jumpers may be used to connect the input pins to VCC and ground. For applications requiring frequent timing adjustment, DIP switches should be used. The enable pin (E) must be at a logic 1 in hardwired implementations. Maximum flexibility is obtained when the eight parallel programming bits are set using computergenerated data. When the data setup (tDSE) and data hold (tDHE) requirements are observed, the enable pin can be used to latch data supplied on an 8-bit bus. Enable must be held at a logic 1 if it is not used to latch the data. After each change in delay value, a settling time (tEDV or tPDV) is required before input logic levels are accurately delayed. Since the DS1020 is a CMOS design, unused input pins (D and C) must be connected to well-defined logic levels; they must not be allowed to float.
SERIAL MODE (S = 0)
In the SERIAL programming mode, the output of the DS1020 will reproduce the logic state of the input after a delay time determined by an 8-bit value clocked into serial port D. While observing data setup (tDSC) and data hold (tDHC) requirements, timing data is loaded in MSB-to-LSB order by the rising edge of the serial clock (C). The enable pin (E) must be at a logic 1 to load or read the internal 8-bit input register, during which time the delay is determined by the last value activated. Data transfer ends and the new delay value is activated when enable (E) returns to a logic 0. After each change, a settling time (tEDV) is required before the delay is accurate. As timing values are shifted into the serial data input (D), the previous contents of the 8-bit input register are shifted out of the serial output pin (Q) in MSB-to-LSB order. By connecting the serial output of one DS1020 to the serial input of a second DS1020, multiple devices can be daisy-chained (cascaded) for programming purposes (Figure 3). The total number of serial bits must be eight times the number of units daisy-chained and each group of 8 bits must be sent in MSB-to-LSB order. Applications can read the setting of the DS1020 delay line by connecting the serial output pin (Q) to the serial input (D) through a resistor with a value of 1k to 10k ohms (Figure 2). Since the read process is destructive, the resistor restores the value read and provides isolation when writing to the device. The resistor must connect the serial output (Q) of the last device to the serial input (D) of the first device of a daisy-chain (Figure 3). For serial readout with automatic restoration through a resistor, the device used to write serial data must go to a high impedance state. To initiate a serial read, enable (E) is taken to a logic 1 while serial clock (C) is at a logic 0. After a waiting time (tEQV), bit 7 (MSB) appears on the serial output (Q). On the first rising (0 1) transition of the serial clock (C), bit 7 (MSB) is rewritten and bit 6 appears on the output after a time tCQV. To restore the input register to its original state, this clocking process must be repeated 8 times. In the case of a daisy-chain, the process must be repeated 8 times per package. If the value read is restored before enable (E) is returned to logic 0, no settling time (tEDV) is required and the programmed delay remains unchanged. Since the DS1020 is a CMOS design, unused input pins (P1 - P7) must be connected to well-defined logic levels; they must not be allowed to float. Serial output Q/P0 should be allowed to float if unused. 2 of 9
DS1020
FUNCTIONAL BLOCK DIAGRAM Figure 1
SERIAL READOUT Figure 2
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DS1020
CASCADING MULTIPLE DEVICES (DAISY CHAIN) Figure 3
PART NUMBER TABLE Table 1
DELAYS AND TOLERANCES (IN ns)
PART NUMBER STEP ZERO DELAY TIME MAX DELAY TIME (NOM) DELAY CHANGE PER STEP (NOM) MAX DEVIATION FROM PROGRAMMED DELAY
DS1020-15 DS1020-25 DS1020-50 DS1020-100 DS1020-200
10 2 10 2 10 2 10 2 10 3
48.25 73.75 137.5 265 520
0.15 0.25 0.5 1 2
4 6 8 20 40
DELAYS VS. PROGRAMMED VALUE Table 2
MIN DELAY STEP ZERO
PARALLEL PORT
BINARY PROGRAMMED VALUE
PART NUMBER DS1020-15 DS1020-25 DS1020-50 DS1020-100 DS1020-200
0 0 0 0 0 0 0 0 10.00 10.00 10.0 10 10
0 0 0 0 0 0 0 1 10.15 10.25 10.5 11 12
0 0 0 0 0 0 1 0 10.30 10.50 11.0 12 14
0 0 0 0 0 0 1 1 10.45 10.75 11.5 13 16
0 0 0 0 0 1 0 0 10.60 11.00 12.0 14 18
0 0 0 0 0 1 0 1 10.75 11.25 12.5 15 20
All delays in nanoseconds, referenced to input pin.
1 1 1 1 1 1 0 1 47.95 73.25 136.5 263 516
1 1 1 1 1 1 1 0 48.10 73.50 137.0 264 518
1 1 1 1 1 1 1 1 48.25 73.75 137.5 265 520
P7 P6 P5 P4 P3 P2 P1 P0
MSB
LSB
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SERIAL PORT
MAX DELAY
DS1020
DALLAS SEMICONDUCTOR TEST CIRCUIT Figure 4
TEST SETUP DESCRIPTION
Figure 4 illustrates the hardware configuration used for measuring the timing parameters of the DS1020. The input waveform is produced by a precision pulse generator under software control. Time delays are measured by a time interval counter (20 ps resolution) connected to the output. The DS1020 serial and parallel ports are controlled by interfaces to a central computer. All measurements are fully automated with each instrument controlled by the computer over an IEEE 488 bus.
TEST CONDITIONS
INPUT: Ambient Temperature: Supply Voltage (VCC): Input Pulse: Source Impedance: Rise and Fall Time: 25C =3C 5.0V =0.1V High = 3.0V =0.1V Low = 0.0V =0.1V 50 ohms max. 3.0 ns max. (measured between 0.6V and 2.4V) Pulse Width: 500 ns (DS1020-15) 500 ns (DS1020-25) 2 s (DS1020-50) 4 s (DS1020-100) 4 s (DS1020-200) 1 s (DS1020-15) 1 s (DS1020-25) 4 s (DS1020-50) 8 s (DS1020-100) 8 s (DS1020-200)
Period:
NOTE: Above conditions are for test only and do not restrict the operation of the device under other data sheet conditions. OUTPUT: Output is loaded with a 74F04. Delay is measured between the 1.5V level of the rising edge of the input signal and the 1.5V level of the corresponding edge of the output.
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DS1020
ABSOLUTE MAXIMUM RATINGS*
Voltage on any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature Short Circuit Output Current -1.0V to +7.0V 0C to 70C -55C to +125C 260C for 10 seconds 50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
PARAMETER Supply Voltage High Level Input Voltage Low Level Input Voltage Input Leakage Current Active Current High Level Output Current Low Level Output Current SYM VCC VIH VIL I1 ICC IOH IOL 0 VI VCC VCC=MAX; PERIOD=1 s VCC=MIN. VOH=2.7V VCC=MIN. VOL=0.5V TEST CONDITION MIN 4.75 2.2 -0.5 -1.0
(0C to 70C; VCC = 5.0V 5%)
TYP 5.00 MAX 5.25 VCC+0.5 0.8 1.0 30.0 -1.0 8 UNITS V V V A mA mA mA 4 3 NOTES 1 1 1
AC ELECTRICAL CHARACTERISTICS
PARAMETER Clock Frequency Enable Width Clock Width Data Setup to Clock Data Hold from Clock Data Setup to Enable Data Hold from Enable Enable to Serial Output Valid Enable to Serial Output High Z Clock to Serial Output Valid Clock to Serial Output Invalid Enable Setup to Clock Enable Hold from Clock Parallel Input Valid to Delay Valid SYMBOL fC tEW tCW tDSC tDHC tDSE tDHE tEQV tEQZ tCQV tCQX tES tEH tPDV 10 50 50 MIN 50 50 30 10 30 20
(0C to 70C; VCC = 5V 5%)
TYP MAX 10 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns ns s NOTES
50 0 50 50
50 6 of 9
DS1020
(cont'd) PARAMETER Parallel Input Change to Delay Invalid Enable to Delay Valid Enable to Delay Invalid VCC Valid to Device Functional Input Pulse Width Input to Output Delay Input Period
SYMBOL tPDX tEDV tEDX tPU tWI tPLH, tPHL Period
MIN 0 0
TYP
MAX 50 100
UNITS ns s ns ms ns
NOTES
100% of Output Delay Table 2 2 (tWI)
ns ns
2
CAPACITANCE
PARAMETER Input Capacitance SYMBOL CIN MIN TYP MAX 10
(TA = 25C)
UNITS pF NOTES
TIMING DIAGRAM: SILICON DELAY LINE Figure 5
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DS1020
TERMINOLOGY
Period: The time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the 1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading edge. tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the input pulse. tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the input pulse. tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input pulse and the 1.5V point on the leading edge of the output pulse. tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input pulse and the 1.5V point on the trailing edge of the output pulse.
TIMING DIAGRAM: NON-LATCHED PARALLEL MODE (S = 1, E = 1) Figure 6
TIMING DIAGRAM: LATCHED PARALLEL MODE (S=1) Figure 7
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DS1020
TIMING DIAGRAM: SERIAL MODE (S = 0) Figure 8
NOTES:
1. All voltages are referenced to ground. 2. @VCC = 5V and 25C. Delay accurate on both rising and falling edges within tolerances given in Table 1. 3. Measured with output open. 4. The "Q" output will only source 4 mA. This pin is only intended to drive other DS1020s.
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